1. Technical Field
This invention relates to dual port SRAMs and, in particular, to a dual port SRAM having a reduced feature size in a rectangular-shaped cell layout.
2. Description of the Related Art
A dual port SRAM circuit is shown in FIG. 1 of a type well known in the art. Dual port SRAMs are particularly advantageous in certain types of memories to allow fast access for reading and writing. For example, dual port SRAMs may be used for the internal memory of a microprocessor in various stack registers. A dual port SRAMs is also frequently used in high speed communications, image processing, a FIFO and other circuits in which high speed and high reliability are required while accessing the memory cell through multiple ports during time periods which may overlap and even occur simultaneously. For these reasons, dual port SRAMs of the circuit type as shown in FIG. 1 have particular benefits across a wide range of products.
Embedded SRAMs are particularly popular for use in high speed communication, image processing, and other applications. SRAMs have the benefit they can hold data without the need for refresh. A standard SRAM cell has two pass gates for transistors through which a bit can be read or written at the same time the complement of the bit is read or written in the other storage node. Dual port SRAMs have four pass gate transistors instead of two pass gates, providing more access to the memory cell. With two ports, the bits stored in the SRAM can be read from two ports, A and B, simultaneously. This allows for parallel operation by different applications. Moreover, if a dual port SRAM has a first SRAM cell and a second SRAM cell in the same column or in the same row, a read operation to the first SRAM cell can be performed simultaneously with a write operation on the second SRAM cell, providing significant benefits in access capabilities.
The details of operation of a dual port SRAM are well known to those of skill in the art and therefore the details need not be repeated here. In summary, data is stored at node 1 and the complement of the data stored at node 2, sometimes called true data and false data, or data and data, written “data bar”. The data can be read from node 1 by enabling the wordline at port A and reading the bitline at port A. In addition, the same data can be accessed by enabling the wordline at port B and reading the data at port B. Similarly, the data stored at node 2, which will be the opposite digital value of the data stored at node 1, can be accessed either through bitline Ā or bitline B when the respective wordlines of port A and port B are enabled.
FIG. 1 shows a standard eight transistor dual port SRAM cell of a type well known in the art. It includes pull up transistors PU-1 and PU-2 which are realized in P-channel transistors. It also includes pull down transistors PD-1 and PD-2. Pass gates PG-1 and PG-3 form a first port, port A, and are controlled by a single wordline labeled Port A WL. Pass gates PG-2 and PG-4 form a second port, port B, and are controlled by the wordline labeled Port B WL. The stored bit can be read through port A using bitlines port ABL and port Ā BL or through port B using bitlines port BBL and port B BL.
There are eight transistors in the particular dual port SRAM of this design, two of which are P-channel transistors labeled PU-1 and PU-2 and the remainder of which are N-channel transistors. Accordingly, the layout of eight transistors to make a single memory cell may sometimes result in the cell taking a relatively large area and also having the necessity for a large number of conductive lines of both polysilicon and metal which must access the memory cell further increasing the size of the memory cell due to the large number of contacts which must have access to the memory cell.
One prior approach in forming a dual port memory cells is described in U.S. Patent Publication No. 2011/0026289 issued to Liaw ('289 Liaw). FIG. 2, as shown herein, is a copy of FIG. 6 of '289 Liaw, which he admitted as prior art to his work. In this layout of the dual port SRAM, the pass gates of port A, PG-1 and PG-3, are one side of the memory cell, in FIG. 2 the right side, while the pass gates for port B, PG-2 and PG-4, are on the opposite, left, side of the memory cell. (Because FIG. 2 is a photocopy from the prior art publication '289 Liaw, it contains many reference numbers and markings from the '289 Liaw application which need not be repeated and described herein. If a tracking of the reference numbers to the Figure as used in FIG. 2 is desired, the reader is directed toward the '289 Liaw publication, which is incorporated herein by reference. In order to maintain clarity, reference numbers used in FIG. 2 of the '289 Liaw publication will not be repeated when describing in the present invention.)
The wordline contacts are spaced far from each other, on opposite sides of the memory cell as well. In addition, the smallest transistors of the memory cell, PU-1 and PU-2, are placed in the center of the memory cell and the active regions thereof are placed in series with the active regions of PD-1 and PD-2 to form nodes 1 and 2, respectively. The result is that the cell is relatively long and narrow with an aspect ratio of greater than 5. Namely, its length is approximately five times greater than that of its width.
FIG. 3 illustrates performance problems which can occur with a prior art layout of the type shown in FIG. 2. FIG. 3 is a copy of FIG. 5A of the '289 Liaw publication. In a memory cell layout of this type, the performance is degraded due to a high wordline capacitance which results in a high wordline RC time constant. One of the causes of this is the large aspect ratio, greater than 5 of the bit cell. If there are many columns, in excess of 300 columns, the performance degrades by greater than 5% based on the aspect ratio alone. Other features of the layout of the memory cell create additional problems.
Some of these problems with this prior art are described in '289 Liaw and therefore not all the figures and the detailed text are repeated herein. In summary, a few of the problems include that, in order to support parallel operation in which two pass gates might be on concurrently or, potentially simultaneously, the transistors PD-1 and PD-2 need to sustain twice the drive current of a pass gate transistor PG. Therefore, the pull down transistors PD-1 must have nearly twice the width and size of the PG transistors. Typically, either an L-shaped region or, as shown in FIG. 2, a T-shaped active region is used to provide the uneven device sizing that is required due to this type of layout in which the pass gates and storage nodes are formed in common in silicon.
While in FIG. 2, the T-shaped active areas located at node 1 and node 2 are shown as having 90° angles at the location where the two lines meet and having sharp corners, in fact, due to optical effects during photolithographic processing, all sharp edges become significantly rounded because the memory cell is being produced at the optical limits of the available wavelength using during the photolithographic process. The result will be rounded edges and that the available width of the transistor is reduce resulting in degraded cell performance. In addition, if a misalignment occurs, the gate electrode of the PG transistors may not be in the expected location unless the width is increased. This will result in a greater mismatch between the pass gates and the other transistors, thus significantly degrading SRAM cell performance. In addition, there will be problems in current grabbing at the intersection junction. Therefore, some portions of PD-1 and PD-2 will have greater current densities than other portions and significant problems further degrading performance and impacting the reliability. In addition, junction linkage is also a problem in a cell layout of this type.
FIG. 4, as shown, illustrates one of the problems of degraded performance of the memory cell when performing a read. FIG. 4 is a copy of the main portions of the transistors from FIG. 2, however, for ease in understanding the illustration of the current flow, only a few of the conductive layers are shown and only some of the main components of the memory cell are labeled in FIG. 4, thus providing a more simplified view of the memory cell from that shown in FIG. 2.
FIG. 4 illustrates one of the problems of the many shortcomings of a memory cell laid out as shown in the prior art of FIG. 2. The read current path for port B is marked by the path shown starting at location 20 at the B-bitline contact and ending at location 22. Data is retrieved from node 1 via electrical connections to the bitline contact at the far left-hand side of the cell. At the same time, the bitline bar data path, namely the complementary data, is obtained from node 2 via the current path shown having a starting location at 24 and ending at 26 passing through node 2. The complementary data, B, is obtained from data path 24 to 26. The particular layout arrangement of FIG. 4 has a redegradation of approximately 14% owing to just the following physical effects. There is extra resistance in the true current path 20 to 22 because the electrical conductor must pass through two contacts marked 28 and 30, which are in series, in addition to having to pass through a long conductor in between 28 and 30 due to the extra resistance of polysilicon passing over a shallow trench isolation for a long distance over the length of more than half of the cell. The extended current path, and having to pass through repeated contacts, contributes to a greater than 10% recurrent loss in device sizes of 28 nm with increasing losses at smaller sizes. In addition, the isolated active regions of pass gates are also impacted by STI stress losses which are greater than 4% of the recurrent at the 28 nm device size. This is just one of the many shortcomings of the memory cell of the prior art.
Note that in FIG. 4, not all of the components are shown and some of the layers are not illustrated for ease in understanding the circuit layout and its operation. More of the layers are shown in FIG. 2, which can be studied together with FIG. 4 to see more of the electrical components present. For a more complete understanding, turn to the prior art publication from which the circuit is taken.
FIG. 5 illustrates the solution that Liaw proposes in his '289 Liaw publication as he shows in his FIG. 7. (FIG. 5 herein is a copy of FIG. 7 in the '289 Liaw, including the reference numbers. The operation of his circuit will not be described herein and thus the reference numbers will not be used; the reader is directed to '289 Liaw to obtain a more full description of the reference numbers and the circuit operation.) The previous FIGS. 1-4 are taken from the '289 Liaw publication as his admitted prior art. His goal is to improve on this design. To make this improvement, he proposes a new design as illustrated in FIG. 5 herein and described in more detail in the '289 Liaw publication with respect to his FIGS. 3 and 7. The solution proposed by Liaw is to add two additional transistors which he labels PD-12 and PD-22. One of his goals in adding two additional transistors is to increase the current flow that can be drawn through the pull down transistors to Vss in his attempt to overcome the current flow problems of the prior art. The addition of two transistors makes his memory cells even larger and more difficult to construct in small geometries.
The design of '289 Liaw is difficult to construct in very small device sizes, such as 28 nm and 20 nm. In addition, the 20 nm technology design rules prohibit two wordline connections at two polypitch heights, therefore his solution is unworkable for small memory cells. Further, additional routing resources are required as compared to the single port bit cells for technologies which prohibit a bidirectional polyline as he uses in his gates, such as the ISDA 20 nm technology design rules. A further problem is the use of metal 1 as the local interconnection to connect two fingers of the pull down transistors. This additional routing requirement makes the cell incompatible with many other memory cells and other transistors to be made on the same device which may not permit use of metal 1 for local interconnects. A yet additional problem is the high aspect ratio of the memory cell. The aspect ratio is well over 5 and approaches 6. This causes a high wordline resistance and increased RC values owing to the skewed shape of the bit cell.